An on resistance of a vertical type power metal oxide semiconductor field effect transistor (MOSFET) depends greatly on an electric resistance of a drift layer. A concentration of an impurity which decides the electric resistance of the drift layer can not be raised up to a critical limit in correspondence to a breakdown voltage of a p-n junction which a base layer and the drift layer form. In accordance with this, a tradeoff relationship exists between the element breakdown voltage and the on resistance. It is important for decreasing an electric power consumption of the MOSFET to improve the tradeoff relationship. The tradeoff relationship has a critical limit which is decided by an element material. In order to decrease the on resistance of the MOSFET further, it is necessary to go beyond this critical limit.
As one means which goes beyond this critical limit, a configuration called as a super junction is employed in the drift layer. The super junction configuration is a configuration in which a p type pillar layer and an n type pillar layer are periodically arranged in a horizontal direction. The super junction configuration can artificially come to a non-doped layer by making charge amounts (amounts of impurities) included in the p type pillar layer and the n type pillar layer equal. As a result, since the drift layer can have the p type pillar layer and the n type pillar layer which have the high impurity concentration while retaining a high breakdown voltage, the MOSFET can have a low on resistance which goes beyond a material limit.
As one example of a method of forming the super junction configuration, there is a multi epitaxial process in which an ion injection into a semiconductor layer and a crystal growth embedding the semiconductor layer are repeated. In general, in the super junction configuration, since it is possible to increase each of the concentrations of the impurities in the p type pillar layer and the n type pillar layer by narrowing a cycle in a transverse direction of the super junction configuration, it is possible to reduce the on resistance. However, in the multi epitaxial process, since the p type pillar layer and the n type pillar layer are formed on the basis of a diffusion of the impurities, it is necessary to make a thickness of a crystal growth layer in one embedding crystal growth thin so as to make the cycle in the transverse direction of the super junction configuration short while maintaining the breakdown voltage of the MOSFET constant. Therefore, a frequency of the embedding crystal growth in the multi epitaxial process is increased.